1. Field of Invention
The present invention relates to a digital loop filter installed in an all-digital phase-locked loop (PLL) for reducing the jitter effect of an input signal to the all-digital PLL as well as reducing the jitter effect of the output signal, such that the all-digital PLL can keep tracking and locking the frequency and phase of the input signal.
2. Description of Related Art
As the consumption and importance of communication products increase and integrated circuits develop rapidly, the demand for communication integrated circuits increases correspondingly, wherein a phase-locked loop (PLL) is one of the common circuits applied for the modulation and demodulation in the communication field and used as a frequency synthesizer on a radio system or a clock signal recovery system with digital circuits.
The principle of the PLL is to track and lock the phase and the frequency of the input signal and the output signal, such that the two signals can be maintained consistently all the time. If the phase error of two signals is equal to zero or very small, then we generally call it is locked. Note that fast lock-in time becomes increasingly important and a necessary feature for the PLL design.
The conventional design of a digital loop filter generally uses an accumulator to average and eliminate the jitter effect of the input signal to the PLL as disclosed in issued patents such as U.S. Pat. No. 7,042,972 issued to Qualcomm, U.S. Pat. No. 7,145,399 issued to Texas Instruments, and a journal entitled “Phase Domain All-Digital Phase-Locked Loop” published in the IEEE Transactions on circuits and systems II on March 2005.
However, the foregoing issued patents and journal adopt the accumulation method to eliminate the jitter effect of an input signal to the PLL, but the accumulator will also record jitter information even when the jitter of the input signal is very large. As a result, the output of the accumulator will become unstable, and the period jitter of the output signal of the PLL cannot be reduced, and thus causing problems to the design of digital loop filters.
In addition, U.S. Pat. No. 5,473,285 entitled “Method and apparatus for performing phase acquisition in an all digital phase lock loop” and issued to Motorola discloses a method of updating an anchor register, and capable of generating a baseline frequency required by the PLL controller. Four consecutive control signals (UP/DOWN) are used for updating the baseline frequency, so as to reduce some of the jitter effect of the input signal on the PLL. However, if the jitter of the input signal is very large, the method of updating an anchor register cannot suppress the jitter effect of the input signal on the PLL effectively, and thus the method cannot reduce the jitter effect of the output signal to the PLL, and the issue of period jitters still exists.